A phase-locked loop (PLL) circuit includes a reference source to provide a reference signal, a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO), and a feedback divider. The output of the voltage controlled oscillator is sent to the feedback divider, which divides the output frequency by an integer. The output of the feedback divider is compared with the reference signal at the phase frequency detector, and the phase difference is used to control a pump-up or pump-down current source in the charge pump to charge or discharge an integrating capacitor in the loop filter. The output voltage of the loop filter is provided to the voltage controlled oscillator to adjust its frequency and phase. The phase-locked loop is a negative feedback loop that is designed so that the frequency of the output of the voltage controlled oscillator is a multiple of that of the reference signal.
A phase-locked loop circuit can track an input frequency or generate a frequency that is a multiple of the input frequency. Phase-locked loop circuits can be used to recover a signal from a noisy communication channel or distribute clock timing pulses in digital circuits.